Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Busby Anton Shilov on March 6, 2020 3:00 PM EST
The latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so Rambus has designed a highly-integrated HBM2E solution for licensing.
The HBM2E standard supports 12-Hi DRAM stacks as well as memory devices of up to 16 Gbps, thus enabling to build up to 24 GB stacks using a 1024-bit bus. At the same time, the new specification officially supports data rates of up to 3.2 Gbps, which results in 409.6 GB/s bandwidth per stack. Rambus’s HBM2E solution includes a controller that can work with 12-Hi KGSDs (known good stack dies) as well as a verified 1024-bit PHY that supports speeds of up to 3.2 Gbps.
The Rambus HBM2E controller core (originally developed by Northwest Logic) is DFI 3.1 compatible (with appropriate extensions) and supports AXI, OCP or proprietary interfaces to connect to integrator logic. Meanwhile, the controller also supports Look-Ahead command processing (a standard way to trim latencies) as well as channel densities of up to 24 Gb.
Licensees of Rambus’s HBM2E solution will get everything they need to integrate it into their designs, including source code of the controller (in a bid to synthesize it for a particular process technology) as well as fully-characterized hard macros (GDSII) of the interface. Alternatively, engineers from Rambus can help integrate the HBM2E IP support for a fee.
- JEDEC Updates HBM2 Memory Standard To 3.2 Gbps; Samsung's Flashbolt Memory Nears Production
- GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+
- Samsung Develops 12-Layer 3D TSV DRAM: Up to 24 GB HBM2
- SK Hynix Announces 3.6 Gbps HBM2E Memory For 2020: 1.8 TB/sec For Next-Gen Accelerators
- Samsung HBM2E ‘Flashbolt’ Memory for GPUs: 16 GB Per Stack, 3.2 Gbps
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azfacea - Friday, March 6, 2020 - linksomething something APU something something
extide - Saturday, March 7, 2020 - linkThey wouldn't need this though, AMD clearly have their own HBM memory controllers.
JasonMZW20 - Saturday, March 7, 2020 - linkAMD licenses Synopsys HBM2 PHYs and controllers. At least, they did for Vega 10/20.
Kurosaki - Friday, March 6, 2020 - linkSue them!!!
Sivar - Friday, March 6, 2020 - linkWhich JEDEC meeting did they steal this from?
rocky12345 - Friday, March 6, 2020 - linkYou beat me to it because I was thinking the same thing.
Spunjji - Thursday, March 12, 2020 - link100%
rocky12345 - Friday, March 6, 2020 - linkMy question is this since they are working with the HBM tech or at least making a controller to work with it have they also licensed themselves to be able to make products work with the HBM2e memory. I only ask because of this companies shading dealings in the past where they sat in the JEDEC meetings years ago then left quickly put out a whole bunch of patents without actually making a product and then sat and waited until memory companies started making and releasing memory products based on the JEDEC spec and Rumpbus then quickly sued pretty much every company they could to suck money from something they basically stole.
To me at least this company is the scum of the scum and I would personally never buy anything they had anything to do with. END OF RANT Ok one more even scum of the earth types most likely think this company is lower than scum...lol
Yojimbo - Friday, March 6, 2020 - linkThey made their witchcraft with newts eyes and toad tongues and puppy dog tails. Beware!
DeeDee - Sunday, May 31, 2020 - linkrocky12345, you're wrong. A little knowledge can be a dangerous thing. Here are the findings
rocky12345, you don't have the slightest idea what you're talking about:
<< In sum, substantial evidence does not support the jury’s verdict that Rambus
breached its duties under the EIA/JEDEC policy. Infineon did not show the first element of
a Virginia fraud action and therefore did not prove fraud associated with the SDRAM
standard. No reasonable jury could find otherwise. The district court erred in denying
JMOL of no fraud on the SDRAM verdict. Because of these holdings, the new trial and
injunction issues are moot. >>
<<Because Infineon did not show that Rambus had a duty to disclose before the DDRSDRAM standard-setting process formally began, the district court properly granted JMOL
of no fraud in Rambus’s favor on the DDR-SDRAM verdict. >>